This invention is directed to semiconductor devices and more particularly to improved static memory cells of the type formed in MOS integrated circuit form.
Static memory devices are preferable over dynamic devices in some types of digital equipment because the refresh overhead inherent in dynamic memories is unnecessary. This is particularly true in microcomputers using relatively small memory arrays where the refresh circuitry would be larger in proportion to the memory circuitry. Static cells traditionally employed six transistor bistable circuits wherein depletion-mode MOS transistors were used as load devices. These cells were much larger in cell area than one transistor cells of dynamic memories, so the density in cells per chip was rather low. Thus, the cost of static memory has been much higher than dynamic. In efforts to reduce the cell size and thus increase cell density on a chip, various improvements have been made in cell layout and manufacturing processes. The design rules or minimum line widths and tolerances have been reduced, and also cell structures which reduce the number of contacts per cell and increase the efficiency in the use of various crossovers and the like have been attempted. One of the major improvements has been the use of implanted polycrystalline silicon resistors as the load devices in the conventional bistable circuit as disclosed in U.S. application Ser. No. 727,116 issued to Rao et al now U.S. Pat. No. 4,110,776 and copending applications Ser. No. 801,699, filed May 31, 1977, by Raymond & Lien, and Ser. No. 910,248, filed May 30, 1978 by McElroy, all assigned to Texas Instruments. Other static memory cell designs which provide higher density and lower power dissipation are shown in pending applications Ser. Nos. 925,891, 925,892, now U.S. Pat. No. 4,198,695, 925,893 and 925,916, now U.S. Pat. No. 4,184,208 all filed July 19, 1978 by Caudel, McElroy, Ponder and Tubbs, respectively, all assigned to Texas Instruments. While very notable improvements have been made, a continuing effort to reduce cell size and simplify manufacture is dictated by the demand for higher density and lower cost.
It is a principal object of this invention to provide improved static memory cells for semiconductor memory devices. Another object is to provide cell designs of high density in MOS static memory arrays. An additional object is to provide improved layout techniques for MOS integrated circuits which permit simplified interconnections using less space on a semiconductor chip.